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    Searched refs:mmCP_HQD_IB_CONTROL (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_0_d.h 590 #define mmCP_HQD_IB_CONTROL 0x325a
gfx_7_2_d.h 603 #define mmCP_HQD_IB_CONTROL 0x325a
gfx_8_0_d.h 653 #define mmCP_HQD_IB_CONTROL 0x325a
gfx_8_1_d.h 653 #define mmCP_HQD_IB_CONTROL 0x325a
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v9_0.c 3451 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
3597 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IB_CONTROL, 0);
amdgpu_gfx_v10_0.c 3343 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
amdgpu_gfx_v7_0.c 3035 mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL);
amdgpu_gfx_v8_0.c 4539 tmp = RREG32(mmCP_HQD_IB_CONTROL);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 2856 #define mmCP_HQD_IB_CONTROL 0x125a
gc_9_1_offset.h 3084 #define mmCP_HQD_IB_CONTROL 0x125a
gc_9_2_1_offset.h 3040 #define mmCP_HQD_IB_CONTROL 0x125a
gc_10_1_0_offset.h 5322 #define mmCP_HQD_IB_CONTROL 0x1fbe
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