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    Searched refs:mmCP_HQD_IQ_TIMER (Results 1 - 13 of 13) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_amdkfd_gfx_v10.c 616 temp = RREG32(mmCP_HQD_IQ_TIMER);
amdgpu_amdkfd_gfx_v7.c 486 temp = RREG32(mmCP_HQD_IQ_TIMER);
amdgpu_amdkfd_gfx_v8.c 484 temp = RREG32(mmCP_HQD_IQ_TIMER);
amdgpu_gfx_v8_0.c 4544 tmp = RREG32(mmCP_HQD_IQ_TIMER);
amdgpu_gfx_v9_0.c 3596 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IQ_TIMER, 0);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_0_d.h 591 #define mmCP_HQD_IQ_TIMER 0x325b
gfx_7_2_d.h 604 #define mmCP_HQD_IQ_TIMER 0x325b
gfx_8_0_d.h 654 #define mmCP_HQD_IQ_TIMER 0x325b
gfx_8_1_d.h 654 #define mmCP_HQD_IQ_TIMER 0x325b
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 2858 #define mmCP_HQD_IQ_TIMER 0x125b
gc_9_1_offset.h 3086 #define mmCP_HQD_IQ_TIMER 0x125b
gc_9_2_1_offset.h 3042 #define mmCP_HQD_IQ_TIMER 0x125b
gc_10_1_0_offset.h 5324 #define mmCP_HQD_IQ_TIMER 0x1fbf
    [all...]

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