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    Searched refs:mmCP_HQD_PQ_BASE (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_amdkfd_gfx_v10.c 545 if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) &&
amdgpu_amdkfd_gfx_v7.c 421 if (low == RREG32(mmCP_HQD_PQ_BASE) &&
amdgpu_amdkfd_gfx_v8.c 416 if (low == RREG32(mmCP_HQD_PQ_BASE) &&
amdgpu_amdkfd_gfx_v9.c 533 if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) &&
amdgpu_gfx_v10_0.c 3408 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
amdgpu_gfx_v9_0.c 3515 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE,
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
polaris10_pwrvirus.h 1509 { 0xb4540fef, mmCP_HQD_PQ_BASE },
1519 { 0xb4540fef, mmCP_HQD_PQ_BASE },
1529 { 0xb4540fef, mmCP_HQD_PQ_BASE },
1539 { 0xb4540fef, mmCP_HQD_PQ_BASE },
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_0_d.h 577 #define mmCP_HQD_PQ_BASE 0x324d
gfx_7_2_d.h 590 #define mmCP_HQD_PQ_BASE 0x324d
gfx_8_0_d.h 640 #define mmCP_HQD_PQ_BASE 0x324d
gfx_8_1_d.h 640 #define mmCP_HQD_PQ_BASE 0x324d
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 2832 #define mmCP_HQD_PQ_BASE 0x124d
gc_9_1_offset.h 3060 #define mmCP_HQD_PQ_BASE 0x124d
gc_9_2_1_offset.h 3016 #define mmCP_HQD_PQ_BASE 0x124d
gc_10_1_0_offset.h 5298 #define mmCP_HQD_PQ_BASE 0x1fb1
    [all...]

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