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    Searched refs:mmCP_HQD_PQ_BASE_HI (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_amdkfd_gfx_v10.c 546 high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI)))
amdgpu_amdkfd_gfx_v7.c 422 high == RREG32(mmCP_HQD_PQ_BASE_HI))
amdgpu_amdkfd_gfx_v8.c 417 high == RREG32(mmCP_HQD_PQ_BASE_HI))
amdgpu_amdkfd_gfx_v9.c 534 high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI)))
amdgpu_gfx_v10_0.c 3410 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
amdgpu_gfx_v9_0.c 3517 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE_HI,
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
polaris10_pwrvirus.h 1510 { 0x00000000, mmCP_HQD_PQ_BASE_HI },
1520 { 0x00000000, mmCP_HQD_PQ_BASE_HI },
1530 { 0x00000000, mmCP_HQD_PQ_BASE_HI },
1540 { 0x00000000, mmCP_HQD_PQ_BASE_HI },
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_0_d.h 578 #define mmCP_HQD_PQ_BASE_HI 0x324e
gfx_7_2_d.h 591 #define mmCP_HQD_PQ_BASE_HI 0x324e
gfx_8_0_d.h 641 #define mmCP_HQD_PQ_BASE_HI 0x324e
gfx_8_1_d.h 641 #define mmCP_HQD_PQ_BASE_HI 0x324e
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 2834 #define mmCP_HQD_PQ_BASE_HI 0x124e
gc_9_1_offset.h 3062 #define mmCP_HQD_PQ_BASE_HI 0x124e
gc_9_2_1_offset.h 3018 #define mmCP_HQD_PQ_BASE_HI 0x124e
gc_10_1_0_offset.h 5300 #define mmCP_HQD_PQ_BASE_HI 0x1fb2
    [all...]

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