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    Searched refs:mmCP_HQD_PQ_CONTROL (Results 1 - 13 of 13) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
polaris10_pwrvirus.h 1515 { 0xc8318509, mmCP_HQD_PQ_CONTROL },
1525 { 0xc8318509, mmCP_HQD_PQ_CONTROL },
1535 { 0xc8318509, mmCP_HQD_PQ_CONTROL },
1545 { 0xc8318509, mmCP_HQD_PQ_CONTROL },
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_0_d.h 586 #define mmCP_HQD_PQ_CONTROL 0x3256
gfx_7_2_d.h 599 #define mmCP_HQD_PQ_CONTROL 0x3256
gfx_8_0_d.h 649 #define mmCP_HQD_PQ_CONTROL 0x3256
gfx_8_1_d.h 649 #define mmCP_HQD_PQ_CONTROL 0x3256
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v10_0.c 3289 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
3414 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
amdgpu_gfx_v9_0.c 3397 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
3521 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_CONTROL,
amdgpu_gfx_v7_0.c 2975 mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
amdgpu_gfx_v8_0.c 4484 tmp = RREG32(mmCP_HQD_PQ_CONTROL);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 2848 #define mmCP_HQD_PQ_CONTROL 0x1256
gc_9_1_offset.h 3076 #define mmCP_HQD_PQ_CONTROL 0x1256
gc_9_2_1_offset.h 3032 #define mmCP_HQD_PQ_CONTROL 0x1256
gc_10_1_0_offset.h 5314 #define mmCP_HQD_PQ_CONTROL 0x1fba
    [all...]

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