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    Searched refs:mmCP_HQD_PQ_WPTR_HI (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_amdkfd_gfx_v10.c 281 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
319 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),
418 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
amdgpu_amdkfd_gfx_v9.c 271 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
309 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),
406 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
amdgpu_gfx_v9_0.c 3500 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3550 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3602 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0);
amdgpu_gfx_v10_0.c 3393 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3443 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 2930 #define mmCP_HQD_PQ_WPTR_HI 0x127c
gc_9_1_offset.h 3158 #define mmCP_HQD_PQ_WPTR_HI 0x127c
gc_9_2_1_offset.h 3114 #define mmCP_HQD_PQ_WPTR_HI 0x127c
gc_10_1_0_offset.h 5396 #define mmCP_HQD_PQ_WPTR_HI 0x1fe0
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