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Searched refs:mmCP_HQD_PQ_WPTR_LO (Results 1 - 8 of 8) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_amdkfd_gfx_v10.c	`317 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),`
amdgpu_amdkfd_gfx_v9.c	`307 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),`
amdgpu_gfx_v9_0.c	`3498 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3548 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3603 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0);`
amdgpu_gfx_v10_0.c	`3391 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3441 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h	`2928 #define mmCP_HQD_PQ_WPTR_LO 0x127b`
gc_9_1_offset.h	`3156 #define mmCP_HQD_PQ_WPTR_LO 0x127b`
gc_9_2_1_offset.h	`3112 #define mmCP_HQD_PQ_WPTR_LO 0x127b`
gc_10_1_0_offset.h	`5394 #define mmCP_HQD_PQ_WPTR_LO 0x1fdf [all...]`

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