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    Searched refs:mmCP_HQD_VMID (Results 1 - 13 of 13) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
polaris10_pwrvirus.h 1514 { 0x00010000, mmCP_HQD_VMID },
1524 { 0x00010000, mmCP_HQD_VMID },
1534 { 0x00010000, mmCP_HQD_VMID },
1544 { 0x00010000, mmCP_HQD_VMID },
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_0_d.h 572 #define mmCP_HQD_VMID 0x3248
gfx_7_2_d.h 585 #define mmCP_HQD_VMID 0x3248
gfx_8_0_d.h 635 #define mmCP_HQD_VMID 0x3248
gfx_8_1_d.h 635 #define mmCP_HQD_VMID 0x3248
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v10_0.c 3447 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
amdgpu_gfx_v7_0.c 3071 for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_MQD_CONTROL; mqd_reg++)
amdgpu_gfx_v8_0.c 4591 for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_HQD_EOP_CONTROL; mqd_reg++)
amdgpu_gfx_v9_0.c 3554 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 2822 #define mmCP_HQD_VMID 0x1248
gc_9_1_offset.h 3050 #define mmCP_HQD_VMID 0x1248
gc_9_2_1_offset.h 3006 #define mmCP_HQD_VMID 0x1248
gc_10_1_0_offset.h 5288 #define mmCP_HQD_VMID 0x1fac
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