HomeSort by: relevance | last modified time | path
    Searched refs:mmCP_HYP_MEC2_UCODE_DATA (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
polaris10_pwrvirus.h 32 #define mmCP_HYP_MEC2_UCODE_DATA 0xf81d
160 { 0x00041b75, mmCP_HYP_MEC2_UCODE_DATA },
161 { 0x000710e8, mmCP_HYP_MEC2_UCODE_DATA },
162 { 0x000910dd, mmCP_HYP_MEC2_UCODE_DATA },
163 { 0x000a1081, mmCP_HYP_MEC2_UCODE_DATA },
164 { 0x000b016f, mmCP_HYP_MEC2_UCODE_DATA },
165 { 0x000c0e3c, mmCP_HYP_MEC2_UCODE_DATA },
166 { 0x000d10ec, mmCP_HYP_MEC2_UCODE_DATA },
167 { 0x000e0188, mmCP_HYP_MEC2_UCODE_DATA },
168 { 0x00101b5d, mmCP_HYP_MEC2_UCODE_DATA },
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_psp_v10_0.c 283 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
amdgpu_psp_v12_0.c 387 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
amdgpu_psp_v3_1.c 463 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
amdgpu_psp_v11_0.c 616 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 6750 #define mmCP_HYP_MEC2_UCODE_DATA 0x581d
gc_9_1_offset.h 6974 #define mmCP_HYP_MEC2_UCODE_DATA 0x581d
gc_9_2_1_offset.h 7002 #define mmCP_HYP_MEC2_UCODE_DATA 0x581d

Completed in 107 milliseconds