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Searched refs:mmCP_ME1_PIPE0_INT_CNTL (Results 1 - 12 of 12) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_0_d.h	`267 #define mmCP_ME1_PIPE0_INT_CNTL 0x3085`
gfx_7_2_d.h	`269 #define mmCP_ME1_PIPE0_INT_CNTL 0x3085`
gfx_8_0_d.h	`300 #define mmCP_ME1_PIPE0_INT_CNTL 0x3085`
gfx_8_1_d.h	`300 #define mmCP_ME1_PIPE0_INT_CNTL 0x3085`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v10_0.c	`4867 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 5080 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);`
amdgpu_gfx_v7_0.c	`4747 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;`
amdgpu_gfx_v8_0.c	`6532 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;`
amdgpu_gfx_v9_0.c	`5409 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h	`2498 #define mmCP_ME1_PIPE0_INT_CNTL 0x1085`
gc_9_1_offset.h	`2772 #define mmCP_ME1_PIPE0_INT_CNTL 0x1085`
gc_9_2_1_offset.h	`2708 #define mmCP_ME1_PIPE0_INT_CNTL 0x1085`
gc_10_1_0_offset.h	`4838 #define mmCP_ME1_PIPE0_INT_CNTL 0x1e25 [all...]`

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