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    Searched refs:mmCP_ME1_PIPE2_INT_CNTL (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_0_d.h 269 #define mmCP_ME1_PIPE2_INT_CNTL 0x3087
gfx_7_2_d.h 271 #define mmCP_ME1_PIPE2_INT_CNTL 0x3087
gfx_8_0_d.h 302 #define mmCP_ME1_PIPE2_INT_CNTL 0x3087
gfx_8_1_d.h 302 #define mmCP_ME1_PIPE2_INT_CNTL 0x3087
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v10_0.c 4873 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
amdgpu_gfx_v7_0.c 4753 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL;
amdgpu_gfx_v8_0.c 6538 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL;
amdgpu_gfx_v9_0.c 5415 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 2502 #define mmCP_ME1_PIPE2_INT_CNTL 0x1087
gc_9_1_offset.h 2776 #define mmCP_ME1_PIPE2_INT_CNTL 0x1087
gc_9_2_1_offset.h 2712 #define mmCP_ME1_PIPE2_INT_CNTL 0x1087
gc_10_1_0_offset.h 4842 #define mmCP_ME1_PIPE2_INT_CNTL 0x1e27
    [all...]

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