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    Searched refs:mmCP_MEC_CNTL (Results 1 - 16 of 16) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_smu8_smumgr.c 199 mmCP_MEC_CNTL);
202 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, tmp);
amdgpu_fiji_smumgr.c 219 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);
amdgpu_polaris10_smumgr.c 115 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v7_0.c 2714 WREG32(mmCP_MEC_CNTL, 0);
2716 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
4676 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
amdgpu_gfx_v10_0.c 2882 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
2884 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
amdgpu_gfx_v8_0.c 4325 WREG32(mmCP_MEC_CNTL, 0);
4327 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
amdgpu_gfx_v9_0.c 3251 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0);
3253 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL,
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
polaris10_pwrvirus.h 54 { 0x50000000, mmCP_MEC_CNTL },
1504 { 0x00000000, mmCP_MEC_CNTL },
1505 { 0x00000000, mmCP_MEC_CNTL },
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_0_d.h 321 #define mmCP_MEC_CNTL 0x208d
gfx_7_2_d.h 324 #define mmCP_MEC_CNTL 0x208d
gfx_8_0_d.h 359 #define mmCP_MEC_CNTL 0x208d
gfx_8_1_d.h 359 #define mmCP_MEC_CNTL 0x208d
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 132 #define mmCP_MEC_CNTL 0x008d
gc_9_1_offset.h 132 #define mmCP_MEC_CNTL 0x008d
gc_9_2_1_offset.h 134 #define mmCP_MEC_CNTL 0x008d
gc_10_1_0_offset.h 2142 #define mmCP_MEC_CNTL 0x0e2d
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