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    Searched refs:mmCP_MQD_BASE_ADDR (Results 1 - 17 of 17) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_amdkfd_gfx_v8.c 233 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_CONTROL; reg++)
234 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
248 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
300 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_DONES; reg++)
amdgpu_amdkfd_gfx_v7.c 260 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++)
261 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
313 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++)
amdgpu_amdkfd_gfx_v10.c 278 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
417 for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
amdgpu_amdkfd_gfx_v9.c 268 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
405 for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
amdgpu_gfx_v7_0.c 3062 /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_MQD_CONTROL */
3072 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
3075 for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++)
3076 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
amdgpu_gfx_v8_0.c 4584 /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_HQD_ERROR */
4592 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
4606 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
4609 for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++)
4610 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
amdgpu_gfx_v10_0.c 3076 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
3398 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
amdgpu_gfx_v9_0.c 3505 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR,
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
polaris10_pwrvirus.h 1507 { 0x54116f00, mmCP_MQD_BASE_ADDR },
1517 { 0x54117300, mmCP_MQD_BASE_ADDR },
1527 { 0x54117700, mmCP_MQD_BASE_ADDR },
1537 { 0x54117b00, mmCP_MQD_BASE_ADDR },
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_0_d.h 569 #define mmCP_MQD_BASE_ADDR 0x3245
gfx_7_2_d.h 582 #define mmCP_MQD_BASE_ADDR 0x3245
gfx_8_0_d.h 632 #define mmCP_MQD_BASE_ADDR 0x3245
gfx_8_1_d.h 632 #define mmCP_MQD_BASE_ADDR 0x3245
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 2816 #define mmCP_MQD_BASE_ADDR 0x1245
gc_9_1_offset.h 3044 #define mmCP_MQD_BASE_ADDR 0x1245
gc_9_2_1_offset.h 3000 #define mmCP_MQD_BASE_ADDR 0x1245
gc_10_1_0_offset.h 5282 #define mmCP_MQD_BASE_ADDR 0x1fa9
    [all...]

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