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    Searched refs:mmCP_MQD_BASE_ADDR_HI (Results 1 - 11 of 11) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
polaris10_pwrvirus.h 1508 { 0x000000b4, mmCP_MQD_BASE_ADDR_HI },
1518 { 0x000000b4, mmCP_MQD_BASE_ADDR_HI },
1528 { 0x000000b4, mmCP_MQD_BASE_ADDR_HI },
1538 { 0x000000b4, mmCP_MQD_BASE_ADDR_HI },
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_0_d.h 570 #define mmCP_MQD_BASE_ADDR_HI 0x3246
gfx_7_2_d.h 583 #define mmCP_MQD_BASE_ADDR_HI 0x3246
gfx_8_0_d.h 633 #define mmCP_MQD_BASE_ADDR_HI 0x3246
gfx_8_1_d.h 633 #define mmCP_MQD_BASE_ADDR_HI 0x3246
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v10_0.c 3077 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3400 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
amdgpu_gfx_v9_0.c 3507 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR_HI,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 2818 #define mmCP_MQD_BASE_ADDR_HI 0x1246
gc_9_1_offset.h 3046 #define mmCP_MQD_BASE_ADDR_HI 0x1246
gc_9_2_1_offset.h 3002 #define mmCP_MQD_BASE_ADDR_HI 0x1246
gc_10_1_0_offset.h 5284 #define mmCP_MQD_BASE_ADDR_HI 0x1faa
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