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Searched refs:mmCP_PQ_WPTR_POLL_CNTL1 (Results 1 - 11 of 11) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_amdkfd_gfx_v10.c	`327 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),`
amdgpu_amdkfd_gfx_v9.c	`315 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_0_d.h	`265 #define mmCP_PQ_WPTR_POLL_CNTL1 0x3084`
gfx_7_2_d.h	`267 #define mmCP_PQ_WPTR_POLL_CNTL1 0x3084`
gfx_8_0_d.h	`298 #define mmCP_PQ_WPTR_POLL_CNTL1 0x3084`
gfx_8_1_d.h	`298 #define mmCP_PQ_WPTR_POLL_CNTL1 0x3084`
/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
polaris10_pwrvirus.h	`1787 { 0x01010101, mmCP_PQ_WPTR_POLL_CNTL1 },`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h	`2496 #define mmCP_PQ_WPTR_POLL_CNTL1 0x1084`
gc_9_1_offset.h	`2770 #define mmCP_PQ_WPTR_POLL_CNTL1 0x1084`
gc_9_2_1_offset.h	`2706 #define mmCP_PQ_WPTR_POLL_CNTL1 0x1084`
gc_10_1_0_offset.h	`4836 #define mmCP_PQ_WPTR_POLL_CNTL1 0x1e24 [all...]`

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