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Searched refs:mmCP_PWR_CNTL_BASE_IDX (Results 1 - 4 of 4) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h	`2478 #define mmCP_PWR_CNTL_BASE_IDX 0`
gc_9_1_offset.h	`2755 #define mmCP_PWR_CNTL_BASE_IDX 0`
gc_9_2_1_offset.h	`2693 #define mmCP_PWR_CNTL_BASE_IDX 0`
gc_10_1_0_offset.h	`4819 #define mmCP_PWR_CNTL_BASE_IDX 0 [all...]`

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