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Searched refs:mmCP_RB0_WPTR_HI (Results 1 - 6 of 6) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v10_0.c	`2801 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 4329 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 4345 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));`
amdgpu_gfx_v9_0.c	`3202 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 4861 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 4877 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h	`2421 #define mmCP_RB0_WPTR_HI 0x1055`
gc_9_1_offset.h	`2698 #define mmCP_RB0_WPTR_HI 0x1055`
gc_9_2_1_offset.h	`2636 #define mmCP_RB0_WPTR_HI 0x1055`
gc_10_1_0_offset.h	`4764 #define mmCP_RB0_WPTR_HI 0x1df5 [all...]`

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