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Searched refs:mmCP_RB1_BASE_HI (Results 1 - 9 of 9) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_0_d.h	`201 #define mmCP_RB1_BASE_HI 0x30b2`
gfx_7_2_d.h	`201 #define mmCP_RB1_BASE_HI 0x30b2`
gfx_8_0_d.h	`225 #define mmCP_RB1_BASE_HI 0x30b2`
gfx_8_1_d.h	`226 #define mmCP_RB1_BASE_HI 0x30b2`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v10_0.c	`2855 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h	`2586 #define mmCP_RB1_BASE_HI 0x10b2`
gc_9_1_offset.h	`2856 #define mmCP_RB1_BASE_HI 0x10b2`
gc_9_2_1_offset.h	`2790 #define mmCP_RB1_BASE_HI 0x10b2`
gc_10_1_0_offset.h	`4924 #define mmCP_RB1_BASE_HI 0x1e52 [all...]`

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