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    Searched refs:mmCP_RB_DOORBELL_CONTROL (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v10_0.c 2751 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2761 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
3044 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
3105 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
amdgpu_gfx_v8_0.c 4239 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
4252 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
amdgpu_gfx_v9_0.c 3220 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
3229 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_8_0_d.h 268 #define mmCP_RB_DOORBELL_CONTROL 0x3059
gfx_8_1_d.h 269 #define mmCP_RB_DOORBELL_CONTROL 0x3059
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 2431 #define mmCP_RB_DOORBELL_CONTROL 0x1059
gc_9_1_offset.h 2708 #define mmCP_RB_DOORBELL_CONTROL 0x1059
gc_9_2_1_offset.h 2646 #define mmCP_RB_DOORBELL_CONTROL 0x1059
gc_10_1_0_offset.h 5028 #define mmCP_RB_DOORBELL_CONTROL 0x1e8d
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