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Searched refs:mmCRTC0_CRTC_CRC_CNTL (Results 1 - 6 of 6) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
amdgpu_dce120_timing_generator.c	`1151 dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_CRC_CNTL, 1193 value = dm_read_reg_soc15(tg->ctx, mmCRTC0_CRTC_CRC_CNTL,`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_8_0_d.h	`693 #define mmCRTC0_CRTC_CRC_CNTL 0x1bd4`
dce_10_0_d.h	`799 #define mmCRTC0_CRTC_CRC_CNTL 0x1bd4`
dce_11_0_d.h	`675 #define mmCRTC0_CRTC_CRC_CNTL 0x1bd4`
dce_11_2_d.h	`682 #define mmCRTC0_CRTC_CRC_CNTL 0x1bd4`
dce_12_0_offset.h	`4216 #define mmCRTC0_CRTC_CRC_CNTL 0x0723 [all...]`

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