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    Searched refs:mmCRTC0_CRTC_GSL_WINDOW (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
amdgpu_dce120_timing_generator.c 266 dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_GSL_WINDOW, tg110->offsets.crtc, 0);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_d.h 513 #define mmCRTC0_CRTC_GSL_WINDOW 0x1B7A
dce_8_0_d.h 847 #define mmCRTC0_CRTC_GSL_WINDOW 0x1b7a
dce_10_0_d.h 975 #define mmCRTC0_CRTC_GSL_WINDOW 0x1b7a
dce_11_0_d.h 787 #define mmCRTC0_CRTC_GSL_WINDOW 0x1b7a
dce_11_2_d.h 836 #define mmCRTC0_CRTC_GSL_WINDOW 0x1b7a
dce_12_0_offset.h 4260 #define mmCRTC0_CRTC_GSL_WINDOW 0x0739
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