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Searched refs:mmCRTC0_CRTC_TEST_PATTERN_CONTROL (Results 1 - 7 of 7) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
amdgpu_dce120_timing_generator.c	`1080 dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_CONTROL, tg110->offsets.crtc, 0); 1092 dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_CONTROL, tg110->offsets.crtc, value);`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_d.h	`547 #define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1BBA`
dce_8_0_d.h	`532 #define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1bba`
dce_10_0_d.h	`615 #define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1bba`
dce_11_0_d.h	`514 #define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1bba`
dce_11_2_d.h	`521 #define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1bba`
dce_12_0_offset.h	`4170 #define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x070b [all...]`

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