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Searched
refs:mmCRTC_GSL_CONTROL
(Results
1 - 10
of
10
) sorted by relevancy
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/
amdgpu_dce80_hw_sequencer.c
50
.crtc = (mmCRTC0_CRTC_GSL_CONTROL -
mmCRTC_GSL_CONTROL
),
53
.crtc = (mmCRTC1_CRTC_GSL_CONTROL -
mmCRTC_GSL_CONTROL
),
56
.crtc = (mmCRTC2_CRTC_GSL_CONTROL -
mmCRTC_GSL_CONTROL
),
59
.crtc = (mmCRTC3_CRTC_GSL_CONTROL -
mmCRTC_GSL_CONTROL
),
62
.crtc = (mmCRTC4_CRTC_GSL_CONTROL -
mmCRTC_GSL_CONTROL
),
65
.crtc = (mmCRTC5_CRTC_GSL_CONTROL -
mmCRTC_GSL_CONTROL
),
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/
amdgpu_dce100_hw_sequencer.c
50
.crtc = (mmCRTC0_CRTC_GSL_CONTROL -
mmCRTC_GSL_CONTROL
),
53
.crtc = (mmCRTC1_CRTC_GSL_CONTROL -
mmCRTC_GSL_CONTROL
),
56
.crtc = (mmCRTC2_CRTC_GSL_CONTROL -
mmCRTC_GSL_CONTROL
),
59
.crtc = (mmCRTC3_CRTC_GSL_CONTROL -
mmCRTC_GSL_CONTROL
),
62
.crtc = (mmCRTC4_CRTC_GSL_CONTROL -
mmCRTC_GSL_CONTROL
),
65
.crtc = (mmCRTC5_CRTC_GSL_CONTROL -
mmCRTC_GSL_CONTROL
),
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/
amdgpu_dce112_hw_sequencer.c
49
.crtc = (mmCRTC0_CRTC_GSL_CONTROL -
mmCRTC_GSL_CONTROL
),
52
.crtc = (mmCRTC1_CRTC_GSL_CONTROL -
mmCRTC_GSL_CONTROL
),
55
.crtc = (mmCRTC2_CRTC_GSL_CONTROL -
mmCRTC_GSL_CONTROL
),
58
.crtc = (mmCRTC3_CRTC_GSL_CONTROL -
mmCRTC_GSL_CONTROL
),
61
.crtc = (mmCRTC4_CRTC_GSL_CONTROL -
mmCRTC_GSL_CONTROL
),
64
.crtc = (mmCRTC5_CRTC_GSL_CONTROL -
mmCRTC_GSL_CONTROL
),
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_hw_sequencer.c
98
.crtc = (mmCRTC0_CRTC_GSL_CONTROL -
mmCRTC_GSL_CONTROL
),
101
.crtc = (mmCRTC1_CRTC_GSL_CONTROL -
mmCRTC_GSL_CONTROL
),
104
.crtc = (mmCRTC2_CRTC_GSL_CONTROL -
mmCRTC_GSL_CONTROL
),
107
.crtc = (mmCRTCV_GSL_CONTROL -
mmCRTC_GSL_CONTROL
),
amdgpu_dce110_timing_generator.c
1306
address = CRTC_REG(
mmCRTC_GSL_CONTROL
);
1378
address = CRTC_REG(
mmCRTC_GSL_CONTROL
);
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_d.h
975
#define
mmCRTC_GSL_CONTROL
0x1B7B
dce_8_0_d.h
853
#define
mmCRTC_GSL_CONTROL
0x1b7b
dce_10_0_d.h
982
#define
mmCRTC_GSL_CONTROL
0x1b7b
dce_11_0_d.h
793
#define
mmCRTC_GSL_CONTROL
0x1b7b
dce_11_2_d.h
842
#define
mmCRTC_GSL_CONTROL
0x1b7b
Completed in 100 milliseconds
Indexes created Tue Oct 28 09:09:52 GMT 2025