HomeSort by: relevance | last modified time | path
    Searched refs:mmCRTC_MASTER_UPDATE_MODE (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/
amdgpu_dce112_hw_sequencer.c 147 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_timing_generator.c 145 dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value);
1711 value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE));
1718 dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value);
amdgpu_dce110_hw_sequencer.c 237 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v11_0.c 2124 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_11_0_d.h 541 #define mmCRTC_MASTER_UPDATE_MODE 0x1bbe
dce_11_2_d.h 548 #define mmCRTC_MASTER_UPDATE_MODE 0x1bbe

Completed in 60 milliseconds