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    Searched refs:mmDCIO_GSL0_CNTL (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_timing_generator.c 1276 dm_write_reg(tg->ctx, CRTC_REG(mmDCIO_GSL0_CNTL), value);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_d.h 1351 #define mmDCIO_GSL0_CNTL 0x1924
dce_8_0_d.h 1294 #define mmDCIO_GSL0_CNTL 0x1924
dce_10_0_d.h 1581 #define mmDCIO_GSL0_CNTL 0x4826
dce_11_0_d.h 1406 #define mmDCIO_GSL0_CNTL 0x4826
dce_11_2_d.h 1486 #define mmDCIO_GSL0_CNTL 0x4826
dce_12_0_offset.h 1874 #define mmDCIO_GSL0_CNTL 0x20a4
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