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    Searched refs:mmDCP5_REGAMMA_CONTROL (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_d.h 2449 #define mmDCP5_REGAMMA_CONTROL 0x49A0
dce_8_0_d.h 2607 #define mmDCP5_REGAMMA_CONTROL 0x49a0
dce_10_0_d.h 3386 #define mmDCP5_REGAMMA_CONTROL 0x44a0
dce_11_0_d.h 3147 #define mmDCP5_REGAMMA_CONTROL 0x44a0
dce_11_2_d.h 4378 #define mmDCP5_REGAMMA_CONTROL 0x44a0
dce_12_0_offset.h 7656 #define mmDCP5_REGAMMA_CONTROL 0x0fe0
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