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    Searched refs:mmDCP_GSL_CONTROL (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_timing_generator.c 1230 uint32_t address = DCP_REG(mmDCP_GSL_CONTROL);
1258 dm_write_reg(tg->ctx, CRTC_REG(mmDCP_GSL_CONTROL), value);
1331 uint32_t address = DCP_REG(mmDCP_GSL_CONTROL);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_d.h 2464 #define mmDCP_GSL_CONTROL 0x1A90
dce_8_0_d.h 2524 #define mmDCP_GSL_CONTROL 0x1a90
dce_10_0_d.h 3303 #define mmDCP_GSL_CONTROL 0x1a90
dce_11_0_d.h 3064 #define mmDCP_GSL_CONTROL 0x1a90
dce_11_2_d.h 4295 #define mmDCP_GSL_CONTROL 0x1a90

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