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Searched refs:mmDC_EDC_STATE_CNT (Results 1 - 6 of 6) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_4_1_offset.h	`129 #define mmDC_EDC_STATE_CNT 0x1191`
gc_9_0_offset.h	`2648 #define mmDC_EDC_STATE_CNT 0x1191`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v9_4.c	`50 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1 }, 133 { "CPC_DC_STATE_RAM_ME1", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT),`
amdgpu_gfx_v9_0.c	`4125 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1}, 5681 { "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT),`
amdgpu_gfx_v8_0.c	`1506 mmDC_EDC_STATE_CNT,`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_8_0_d.h	`2824 #define mmDC_EDC_STATE_CNT 0x3191`

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