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    Searched refs:mmDC_GPIO_SYNCA_MASK (Results 1 - 11 of 11) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_ci_baco.c 57 { CMD_READMODIFYWRITE, mmDC_GPIO_SYNCA_MASK, 0, 0, 0, 0x00001111 }
amdgpu_fiji_baco.c 55 { CMD_READMODIFYWRITE, mmDC_GPIO_SYNCA_MASK, 0, 0, 0, 0x00001111 }
amdgpu_polaris_baco.c 54 { CMD_READMODIFYWRITE, mmDC_GPIO_SYNCA_MASK, 0, 0, 0, 0x00001111 }
amdgpu_tonga_baco.c 55 { CMD_READMODIFYWRITE, mmDC_GPIO_SYNCA_MASK, 0, 0, 0, 0x00001111 }
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_d.h 1277 #define mmDC_GPIO_SYNCA_MASK 0x1964
dce_8_0_d.h 1365 #define mmDC_GPIO_SYNCA_MASK 0x1964
dce_10_0_d.h 1656 #define mmDC_GPIO_SYNCA_MASK 0x4884
dce_11_0_d.h 1486 #define mmDC_GPIO_SYNCA_MASK 0x4884
dce_11_2_d.h 1585 #define mmDC_GPIO_SYNCA_MASK 0x4884
dce_12_0_offset.h 2026 #define mmDC_GPIO_SYNCA_MASK 0x2102
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/
dcn_1_0_offset.h     [all...]

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