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Searched refs:mmDC_GPU_TIMER_READ_BASE_IDX (Results 1 - 4 of 4) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/
dcn_1_0_offset.h	`1077 #define mmDC_GPU_TIMER_READ_BASE_IDX 2 [all...]`
dcn_2_1_0_offset.h	`713 #define mmDC_GPU_TIMER_READ_BASE_IDX 2 [all...]`
dcn_2_0_0_offset.h	`751 #define mmDC_GPU_TIMER_READ_BASE_IDX 2 [all...]`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_12_0_offset.h	`1885 #define mmDC_GPU_TIMER_READ_BASE_IDX 2 [all...]`

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