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Searched refs:mmDC_GPU_TIMER_READ_CNTL (Results 1 - 9 of 9) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_d.h	`1280 #define mmDC_GPU_TIMER_READ_CNTL 0x192A`
dce_8_0_d.h	`1300 #define mmDC_GPU_TIMER_READ_CNTL 0x192a`
dce_10_0_d.h	`1587 #define mmDC_GPU_TIMER_READ_CNTL 0x482c`
dce_11_0_d.h	`1412 #define mmDC_GPU_TIMER_READ_CNTL 0x482c`
dce_11_2_d.h	`1492 #define mmDC_GPU_TIMER_READ_CNTL 0x482c`
dce_12_0_offset.h	`1886 #define mmDC_GPU_TIMER_READ_CNTL 0x20aa [all...]`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/
dcn_1_0_offset.h	`1078 #define mmDC_GPU_TIMER_READ_CNTL 0x0129 [all...]`
dcn_2_1_0_offset.h	`714 #define mmDC_GPU_TIMER_READ_CNTL 0x0129 [all...]`
dcn_2_0_0_offset.h	`752 #define mmDC_GPU_TIMER_READ_CNTL 0x0129 [all...]`

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