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    Searched refs:mmDC_HPD1_INT_CONTROL (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v6_0.c 269 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
274 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
310 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
312 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
2889 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2891 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2894 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2896 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
3083 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
3085 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp)
    [all...]
amdgpu_dce_v8_0.c 263 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
268 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
304 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
306 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
2979 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2981 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2984 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2986 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
3173 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
3175 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_d.h 1285 #define mmDC_HPD1_INT_CONTROL 0x1808
dce_8_0_d.h 3515 #define mmDC_HPD1_INT_CONTROL 0x1808

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