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Searched refs:mmDP0_DP_DPHY_BS_SR_SWAP_CNTL (Results 1 - 9 of 9) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/
amdgpu_dce100_resource.c	`91 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC`
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_resource.c	`98 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC`
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/
amdgpu_dce112_resource.c	`90 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_11_0_d.h	`4559 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4adc`
dce_11_2_d.h	`5791 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4adc`
dce_12_0_offset.h	`[all...]`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/
dcn_1_0_offset.h	`8449 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144 [all...]`
dcn_2_1_0_offset.h	`9953 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144 [all...]`
dcn_2_0_0_offset.h	`[all...]`

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