HomeSort by: relevance | last modified time | path
    Searched refs:mmDPGV0_WATERMARK_MASK_CONTROL (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_mem_input_v.c 724 mmDPGV0_WATERMARK_MASK_CONTROL,
810 mmDPGV0_WATERMARK_MASK_CONTROL,
913 mmDPGV0_WATERMARK_MASK_CONTROL,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_11_0_d.h 6613 #define mmDPGV0_WATERMARK_MASK_CONTROL 0x4732
dce_11_2_d.h 7926 #define mmDPGV0_WATERMARK_MASK_CONTROL 0x4732

Completed in 51 milliseconds