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Searched refs:mmGB_MACROTILE_MODE0 (Results 1 - 12 of 12) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vi.c	`535 {mmGB_MACROTILE_MODE0}, 630 case mmGB_MACROTILE_MODE0: 646 idx = (reg_offset - mmGB_MACROTILE_MODE0);`
amdgpu_cik.c	`1029 {mmGB_MACROTILE_MODE0}, 1125 case mmGB_MACROTILE_MODE0: 1141 idx = (reg_offset - mmGB_MACROTILE_MODE0);`
amdgpu_gfx_v8_0.c	`2284 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); 2474 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); 2663 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); 2866 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); 3068 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); 3239 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); 3416 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);`
amdgpu_gfx_v7_0.c	`1227 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1410 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1580 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_0_d.h	`726 #define mmGB_MACROTILE_MODE0 0x2664`
gfx_7_2_d.h	`739 #define mmGB_MACROTILE_MODE0 0x2664`
gfx_8_0_d.h	`811 #define mmGB_MACROTILE_MODE0 0x2664`
gfx_8_1_d.h	`811 #define mmGB_MACROTILE_MODE0 0x2664`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h	`1008 #define mmGB_MACROTILE_MODE0 0x0664`
gc_9_1_offset.h	`978 #define mmGB_MACROTILE_MODE0 0x0664`
gc_9_2_1_offset.h	`944 #define mmGB_MACROTILE_MODE0 0x0664`
gc_10_1_0_offset.h	`2922 #define mmGB_MACROTILE_MODE0 0x1404 [all...]`

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