HomeSort by: relevance | last modified time | path
    Searched refs:mmGDS_VMID0_BASE (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v10_0.c 1625 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
1643 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
3953 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
amdgpu_gfx_v9_0.c 2433 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
2451 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4009 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
4169 WREG32_SOC15(GC, 0, mmGDS_VMID0_BASE, 0x00000000);
amdgpu_gfx_v7_0.c 103 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
amdgpu_gfx_v8_0.c 186 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_0_d.h 2219 #define mmGDS_VMID0_BASE 0x3300
gfx_7_2_d.h 2241 #define mmGDS_VMID0_BASE 0x3300
gfx_8_0_d.h 2439 #define mmGDS_VMID0_BASE 0x3300
gfx_8_1_d.h 2418 #define mmGDS_VMID0_BASE 0x3300
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 3040 #define mmGDS_VMID0_BASE 0x1300
gc_9_1_offset.h 3270 #define mmGDS_VMID0_BASE 0x1300
gc_9_2_1_offset.h 3220 #define mmGDS_VMID0_BASE 0x1300
gc_10_1_0_offset.h 5522 #define mmGDS_VMID0_BASE 0x20a0
    [all...]

Completed in 141 milliseconds