HomeSort by: relevance | last modified time | path
    Searched refs:mmGRBM_GFX_CNTL (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_4_1_offset.h 76 #define mmGRBM_GFX_CNTL 0x0022
gc_9_0_offset.h 80 #define mmGRBM_GFX_CNTL 0x0022
gc_9_1_offset.h 80 #define mmGRBM_GFX_CNTL 0x0022
gc_9_2_1_offset.h 78 #define mmGRBM_GFX_CNTL 0x0022
gc_10_1_0_offset.h 2088 #define mmGRBM_GFX_CNTL 0x0dc2
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
soc15_common.h 106 uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; \
amdgpu_nv.c 151 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
amdgpu_soc15.c 300 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
amdgpu_gfx_v10_0.c 2740 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
2743 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);

Completed in 105 milliseconds