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    Searched refs:mmGRBM_GFX_CNTL_BASE_IDX (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_4_1_offset.h 77 #define mmGRBM_GFX_CNTL_BASE_IDX 0
gc_9_0_offset.h 81 #define mmGRBM_GFX_CNTL_BASE_IDX 0
gc_9_1_offset.h 81 #define mmGRBM_GFX_CNTL_BASE_IDX 0
gc_9_2_1_offset.h 79 #define mmGRBM_GFX_CNTL_BASE_IDX 0
gc_10_1_0_offset.h 2089 #define mmGRBM_GFX_CNTL_BASE_IDX 0
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
soc15_common.h 106 uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; \

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