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    Searched refs:mmGRBM_PWR_CNTL2_BASE_IDX (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_4_1_offset.h 83 #define mmGRBM_PWR_CNTL2_BASE_IDX 0
gc_9_0_offset.h 87 #define mmGRBM_PWR_CNTL2_BASE_IDX 0
gc_9_1_offset.h 87 #define mmGRBM_PWR_CNTL2_BASE_IDX 0
gc_9_2_1_offset.h 85 #define mmGRBM_PWR_CNTL2_BASE_IDX 0
gc_10_1_0_offset.h 2093 #define mmGRBM_PWR_CNTL2_BASE_IDX 0
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