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    Searched refs:mmIH_VMID_0_LUT (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
osssys_4_0_1_offset.h 30 #define mmIH_VMID_0_LUT 0x0000
osssys_4_0_offset.h 30 #define mmIH_VMID_0_LUT 0x0000
osssys_5_0_0_offset.h 30 #define mmIH_VMID_0_LUT 0x0000
oss_2_4_d.h 29 #define mmIH_VMID_0_LUT 0xe00
oss_2_0_d.h 29 #define mmIH_VMID_0_LUT 0xf50
oss_3_0_1_d.h 29 #define mmIH_VMID_0_LUT 0xe00
oss_3_0_d.h 29 #define mmIH_VMID_0_LUT 0xe00
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_amdkfd_gfx_v10.c 183 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid,
amdgpu_amdkfd_gfx_v7.c 195 WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);
amdgpu_amdkfd_gfx_v8.c 153 WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);
amdgpu_amdkfd_gfx_v9.c 177 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid,
amdgpu_gmc_v10_0.c 512 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
amdgpu_gmc_v7_0.c 505 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
amdgpu_gmc_v9_0.c 677 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
amdgpu_gmc_v8_0.c 707 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);

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