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    Searched refs:mmMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/mmhub/
mmhub_1_0_offset.h 1747 #define mmMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 0
mmhub_9_1_offset.h 1779 #define mmMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 0
mmhub_9_3_0_offset.h 1763 #define mmMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 0
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 5949 #define mmMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1
gc_9_1_offset.h 6171 #define mmMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1
gc_9_2_1_offset.h 6135 #define mmMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1

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