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    Searched refs:mmMMMC_VM_MX_L1_TLB_CNTL (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_mmhub_v2_0.c 111 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
123 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
291 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
295 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/mmhub/
mmhub_2_0_0_offset.h 1780 #define mmMMMC_VM_MX_L1_TLB_CNTL 0x0873

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