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    Searched refs:mmMP0PUB_IND_INDEX_0 (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
smu_8_0_d.h 195 #define mmMP0PUB_IND_INDEX_0 0x180
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_smu8_smumgr.c 132 cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX_0,

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