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Searched refs:mmPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/
dcn_1_0_offset.h	`517 #define mmPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1 [all...]`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_12_0_offset.h	`709 #define mmPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1 [all...]`

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