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Searched refs:mmPLL_CNTL (Results 1 - 5 of 5) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_ci_baco.c	`96 { CMD_READMODIFYWRITE, mmPLL_CNTL, PLL_CNTL__PLL_RESET_MASK, PLL_CNTL__PLL_RESET__SHIFT, 0, 0x1 }, 97 { CMD_READMODIFYWRITE, mmPLL_CNTL, PLL_CNTL__PLL_POWER_DOWN_MASK, PLL_CNTL__PLL_POWER_DOWN__SHIFT, 0, 0x1 }, 98 { CMD_READMODIFYWRITE, mmPLL_CNTL, PLL_CNTL__PLL_BYPASS_CAL_MASK, PLL_CNTL__PLL_BYPASS_CAL__SHIFT, 0, 0x1 },`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_d.h	`4061 #define mmPLL_CNTL 0x1707`
dce_8_0_d.h	`1121 #define mmPLL_CNTL 0x1707`
dce_10_0_d.h	`6079 #define mmPLL_CNTL 0x1707`
dce_11_0_d.h	`6156 #define mmPLL_CNTL 0x1707`

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