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    Searched refs:mmRLC_GPM_SCRATCH_DATA (Results 1 - 11 of 11) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v9_0.c 2669 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
2675 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2679 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2680 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2684 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j);
2699 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
2705 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
amdgpu_gfx_v7_0.c 3895 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3896 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3897 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
3901 WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
3906 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
amdgpu_gfx_v8_0.c 3989 WREG32(mmRLC_GPM_SCRATCH_DATA, register_list_format[i]);
3994 WREG32(mmRLC_GPM_SCRATCH_DATA, list_size);
4000 WREG32(mmRLC_GPM_SCRATCH_DATA,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_0_d.h 1319 #define mmRLC_GPM_SCRATCH_DATA 0x312d
gfx_7_2_d.h 1332 #define mmRLC_GPM_SCRATCH_DATA 0x312d
gfx_8_0_d.h 1432 #define mmRLC_GPM_SCRATCH_DATA 0xec6d
gfx_8_1_d.h 1429 #define mmRLC_GPM_SCRATCH_DATA 0xec6d
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 6108 #define mmRLC_GPM_SCRATCH_DATA 0x4c6d
gc_9_1_offset.h 6330 #define mmRLC_GPM_SCRATCH_DATA 0x4c6d
gc_9_2_1_offset.h 6308 #define mmRLC_GPM_SCRATCH_DATA 0x4c6d
gc_10_1_0_offset.h     [all...]

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