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    Searched refs:mmRLC_GPM_TIMER_INT_3 (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v9_0.c 2962 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 5992 #define mmRLC_GPM_TIMER_INT_3 0x4c15
gc_9_1_offset.h 6214 #define mmRLC_GPM_TIMER_INT_3 0x4c15
gc_9_2_1_offset.h 6178 #define mmRLC_GPM_TIMER_INT_3 0x4c15
gc_10_1_0_offset.h 9304 #define mmRLC_GPM_TIMER_INT_3 0x4c15
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