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    Searched refs:mmRLC_GPR_REG2 (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v7_0.c 3445 WREG32(mmRLC_GPR_REG2, tmp);
3456 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
3467 WREG32(mmRLC_GPR_REG2, tmp);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_0_d.h 1324 #define mmRLC_GPR_REG2 0x313a
gfx_7_2_d.h 1337 #define mmRLC_GPR_REG2 0x313a
gfx_8_0_d.h 1437 #define mmRLC_GPR_REG2 0xec7a
gfx_8_1_d.h 1434 #define mmRLC_GPR_REG2 0xec7a
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 6126 #define mmRLC_GPR_REG2 0x4c7a
gc_9_1_offset.h 6348 #define mmRLC_GPR_REG2 0x4c7a
gc_9_2_1_offset.h 6326 #define mmRLC_GPR_REG2 0x4c7a
gc_10_1_0_offset.h 9446 #define mmRLC_GPR_REG2 0x4c7a
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