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    Searched refs:mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 6031 #define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX 1
gc_9_1_offset.h 6253 #define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX 1
gc_9_2_1_offset.h 6229 #define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX 1
gc_10_1_0_offset.h 9353 #define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX 1
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