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Searched refs:mmRLC_LB_THR_CONFIG_3 (Results 1 - 4 of 4) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v9_0.c	`1720 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); 1769 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h	`6228 #define mmRLC_LB_THR_CONFIG_3 0x4cb9`
gc_9_1_offset.h	`6450 #define mmRLC_LB_THR_CONFIG_3 0x4cb9`
gc_9_2_1_offset.h	`6426 #define mmRLC_LB_THR_CONFIG_3 0x4cb9`

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